1) The Enhanced Orring Diode
When converters are paralleled, they can offer a number of useful features;a) potential redundancyIn order to maintain redundancy and avoid the reduced reliability that a generally increased total parts count would entail, paralleled sections must be fault-isolated. This allows for a failure in one section that does not reduce the ability of others to function normally.
b) versatility of configuration and scale
c) inventory part type reduction
d) noise reduction and filtering cost/size reduction
At the load, this will generally involve the use of orring diodes at module power levels. While special low-voltage drop schottky semiconductors have been developed for this function, the best efficiency is still obtained using active switches with a lower voltage drop, particularly when supplying lower bus voltages.
..........and one attempt to employ Pmos fets to reduce losses.
There are many ways to implement semiconductor switches in the orring diode position, all capable of offering varying degrees of success in a particular application. The control for these switches should, however, provide the same protection afforded by the simple diode configuration for single faults, including faults in the switch control section, or they cannot provide the intended fault isolation.
1) Natural defaults - Mosfets have internal body diodes which can perform the orring diode function, in the absence or failure of the intended control method. An orring diode is compromised if it is used additionally as a hard enable line.
2) Enhancement - The forward drop of a mosfet can be reduced by providing gate bias. This is a very low power control requirement, providing that only static operation is needed. It is required only in the event of body diode forward current flow, and need only appear as quickly as thermal system configuration demands.
3) Predictability - Losses in the enhanced mode are resistive and will produce a predictable worst-case forward voltage drop at the module rating, depending on device type and gate voltage. Obtaining significantly lower forward voltage drops at reduced currents is tempting, but may not always be in the best interest of the system regulation or sharing control.
4) Transient Blocking Function - In order to duplicate the protection function of the diode, enhancement must be removed before significant reverse current occurs under source internal fault or 'reverse' conditions. The blocking function must occur very quickly, and may depend only on inductances inadvertently present in hardware and wiring; these are potentially the only restrictions on the change of current flow (~ into the converter's internal fault) with the exception of decoupling capacitor ESR.
In the simplest application, the voltage drop across the fet is regulated at 1/10th the reference voltage. If lower (or negative) voltages are generated by load current flow, enhancement is removed. Bias for the amplifier and reference require the usual 'sky-hook' supply seen in many application notes, but one that is not difficult to provide in most active converters, at this milliwatt power level. This bias supply must be sufficiently high so as to enhance the nmos fet gate used in this illustration.
Removal of either converter power or control power removes the gate enhancement. As the voltage on the rectifier naturally attempts to reduce as current reduces, the regulator reacts on sensed voltage values prior to the zero-current condition: the potential for extremely fast turn-off is therefore presented. As the gate voltage is normally biased around the threshold value, a minimum charge is stored in the gate capacitances.
At low frequencies, controllers with suitable bandwidth will be capable of reducing load-induced voltage transients occurring across the orring diode position, reducing local buss capacitance requirements on the output side of the orring circuit. It is interesting to vary the load and to note the gate bias voltage tracking load current changes, below the saturating RDSon value of the mosfet.
As this is a linear mode of operation, paralleled fets will not share outside the saturation region. Sharing, if intended, must be enforced by regular means, unless the regulated forward drop is modified so as to be included in such a control scheme. As the orring regulated voltage is exceeded by the saturation voltage at increasing current, gate drive will peg at its limit. As current increases to force the voltage drop to equal the forward bias of parasitic body diodes, they will act as simple rectifiers, with the normal imbalances associated with a negative forward voltage temperature coefficient.
A simulation of a hard short across the converter rails, on the converter side of the orring diode, shows the type of response required, as capacitor currents flow under limit of local ESR only - both the converter output and the load input being capacitive in this worst-case scenario.
Stray inductances of 40nH are assumed to couple the orring section output and any local decoupling capacitors from the point of load. While in reality the most likely short circuit fault in a high frequency converter secondary will be in the rectifiers, isolated from the orring circuit by a specified filter inductance, only the local value of wiring strays is used here.
2) Normally-Off Synchronous Rectifier
The peak surge current and itís duration can be used as figures of merit for circuit response to this worst-case protective fault condition. Considering that the simulation employs a jellybean low-power op-amp of the LM358 variety, while still achieving rectifier function in some 100s of nanoseconds, the results are encouraging. In real hardware trials, the values typically improve.
The concept is not restricted to low frequency applications - it is limited only by the designer's ingenuity and access to suitable small-signal hardware, within budget. It is an obvious candidate for integration and has been applied to output rectifiers above 100KHz, using discrete components.3) Integration examples:
As gate enhancement is always applied only after drain voltages are less than zero and is always removed prior to current reversal, gate drive energy is limited to that required by both Zero-Voltage and Zero-Current switching regimes. Reverse transfer capacitance energy is always absorbed when the gate driver is active low. If the drive transitions are completed in a timely manner, the mosfet sees little switching loss and it's body diode does not pass current or store reverse recovery charge.
A number of integrated controllers are currently available to perform this function - all rely on switching the synchronous rectifier based on external stimulus, rather than simple linear terminal voltage regulation.
NIS6111: (050325 note) ON Semiconductor appears to have developed this circuit as an integrated device, in the NIS6111. Haven't tried it, but there's no reason it shouldn't work, if properly engineered. The final control method in the NIS6111 is digital vs linear, which may introduce interesting modes of operation at lower currents and in 'noisy' situations.
NIS6111 data sheet : http://www.onsemi.com/pub_link/Collateral/NIS6111-D.PDF
App Notes : http://www.onsemi.com/PowerSolutions/supportDoc.do?type=AppNotes&rpn=NIS6111
Look for AND8174-D, AND8183-D, AND8188-D, AND8189-D and AND8194-D on the web.
One interesting feature of the ON Semi application documents, are the single fault waveforms. The di/dt recorded there is indicative of 600nH stray inductance. How this inductance is accumulated in the demo board layout is an interesting puzzle.
It is unfortunate that the control section of the 'hybrid' was not marketed separately, without the added cost of power packaging (PLLP32/488AC leadless surface mount chip) and without introducing the added complication of the fixed internal device, in the multi-fet situations suggested in documentation.
Note 100916: - NIS6111 and all app literature withdrawn from ON website in ~2008.
IR5001: (050512 note) International Rectifier now offers an integrated controller that serves a similar function at telecom bus voltages (-36 to -75Vdc). The IR5001s is aimed at offering power from multiple 48V bus sources to a single load, through the body diode of an NMosfet.
It is one application that avoids the need for 'skyhook' bias supplies, as it draws power from the 'output' of the orring device. This is possible because the negative output terminal is not used as a common ground reference.
IR5001s data sheet : http://www.irf.com/product-info/datasheets/data/ir5001s.pdf
IRAC5001 EV board : http://www.irf.com/technical-info/refdesigns/irac5001-hs100a.pdf
Curiously, IR somehow manages to introduce almost 10uH of interconnect strays, as depicted in its fault test waveforms - either that or the time references in the EV Board app note's fig 6b are incorrect, giving an apparent di/dt into the applied test short of less than 1A/uSec.(rev1.3 dated 040308). Fig 6c actually shows an unexplained dual slope current waveform, and a current discontinuity lasting for three scope divisions, with the same di/dt limit at it's steepest point. Even if the time scale has been amplified by a factor of 5 (200mS/S), you'd not normally find 2uH of stray inductance in such a scheme.
Again, this is a digital control function. Though hysterisis is present, it can never be large enough to overcome the natural increases in Vds, generated by it's own turn-off activity. In fact, if the spec sheet is correct, the enhancement isn't removed until the drain voltage actually becomes positive (fig3).
This means that forward current through the fully enhanced part is required, simply to turn it off.
IR1167A: (060502 note) IR has taken a second run at the application, and produced their nearest approach to the simple circuit required. Unfortunately, no attempt is made in AN-1087 to evaluate the part as a simple orring diode, or to record it's ability to block single fault currents. This would be a basic limiting figure of merit for such devices, in any direct comparison, once simple circuit function is demonstrated.
IR1167as - IR1167bs data sheet : http://www.irf.com/product-info/datasheets/data/ir1167aspbf.pdf
IR1167 App Note : http://www.irf.com/technical-info/appnotes/an-1087.pdf
- The introduction of nonlinear (comparator-controlled switching with hysterisis) and arbitrary gate control (blanking and minimum on timing) is only likely to produce spurious responses - not defeat them.
- By failing to provide a suitable low impedance termination to ground in the off or single-fault situation, the fet is being prevented from functioning as a 'simple' rectifier during start-up, limiting or other common situations.
IR11672: was introduced in 2009 with an 'MOT protection mode' feature in it's state machine. This basically removes enhancement control on a cycle-skipping basis, when excess on-time is somehow detected. Sound predictable? Think it works?
IR11672 data sheet : http://www.irf.com/product-info/datasheets/data/ir11672aspbf.pdf
IR11672 app note : https://ec.irf.com/sales/know_sheet/KS10772.pdf
ISL6144: (081012 note) Intersil now offers a 16 and 20-pin IC with an internal charge pump, 75V operating range, hysteretic and timed digital gate control and various status signals - this for a device that should require no more than 4pins for this basically linear function. This seriously affects itís suitability for economical employment, whether or not it can perform as intended.
ISL6144 data: http://www.intersil.com/data/fn/fn9131.pdf
ISL6144 eval board: http://www.intersil.com/data/an/an1129.pdf
ZXGD3101: (090912 note) An 8-pin SO-8 package by Zetex (Diodes Inc), released in early 2009, comes closest to the simple linear control concept. Developed and marketed to control the output rectifier of off-line flyback circuits, it still differentiates the linear control of the gate from non-linear switching events at turn-on and turn-off.
Between 50 and 200mV of sensed Vsd, gate voltages of between 7.5V and 9.5V are supplied. When the sense voltage falls below 24mV, the non-linear turn-off is enforced. There is no explanation of what happens when this non-linear turn-off behavior results in an increased Vsd, although it appears that turn-on behavior may require 600mV or more to be triggered.
Setting an arbitrary gate threshold voltage range is non-intuitive, if a wide variety of mosfet devices is anticipated. The 24mV non-linear turn-off threshold Ė which is adjustable by setting a bias current differential on two external IC pins Ė is not what is required. What needs to be adjustable is the regulated forward voltage drop. Turn-off behavior would then be naturally-occurring for all devices employed, and suitable gate enhancement levels automatically developed. The aim should not be simply to replace ultrafast rectifiers in 3A flyback circuits, but all rectifiers, including schottkies, wherever practical.
What is encouraging here is the development and use of fairly accurate, internally-integrated sensing of low negative voltages on the drain. This occurs through a single chip pin that withstands +180V drain excursions while providing 3V of operating compliance below chip ground. This is some achievement.
Lets hope that this feature is not the only one that prevented the development of semiconductor die sizes that would be suited to commercialization in the smaller SC74/SOT25 lead frames.
ZXGD3101 data : http://www.diodes.com/datasheets/ZXGD3101.pdf
ZXGD3101 application : http://www.diodes.com/_files/products_appnote_pdfs/zetex/an54.pdf
resonant application : http://www.diodes.com/_files/products_appnote_pdfs/zetex/an69_v3.pdf
Virtually the same circuit is offered as ZXGD3102, for orring diode applications, including those targeted by IR5001 in 48V telecom rectifier converters.
ZXGD3102 data : http://www.diodes.com/datasheets/ZXGD3102.pdf
ZXGD3103: , an advanced version of ZXGD3101, was introduced in July 2010. This offers reduced drive currents (4/7 to 2.5/6A source/sink) and reduced turn-off threshold sensing voltages (-45 to -16mV). Both of these issues are avoided or made irrelevant in a straight linear application.
ZXGD3103 data : http://www.diodes.com/datasheets/ZXGD3103N8.pdf
LTC4354, LTC4355, LTC4357, LTC4358:
Seem to have missed some important ones here, from 2008.
LTC4345: is an 8-pin dual orring NMOS controller targeted for negative sources between 4.5 and 80V, the same Telecom range as the single device controller IR5001, using the same load-generated housekeeping supply voltage. The drain voltage sensing pins exhibit an 80V compliance with respect to the source terminal, in spite of an internal Vcc clamp of 11V, but are only rated for 300mV in the third quadrant. Turn-off times are an abysmal 700nS in the faulted-source condition; turn-on time approximately 1mS. These features would prevent the controller from being used in a basic grounded NMOS fet rectifier.
Despite the confusing description on page 5 of the spec, the functional diagram illustrates a simple linear control function, at a Vds of ~30mV. This is unrealistically low: 150 or 200mV would have preserved the linear function without developing an increased worst-case loss in the IRF3710 control application. (a 100V 24mR TO263/D2 part). A fault detection indication is present.
LTC4354 data: http://cds.linear.com/docs/Datasheet/4354fb.pdf
LTC4354 app: http://cds.linear.com/docs/Reference%20Design/dc852A.pdf
LTC4355: is a 16-pin dual orring NMOS controller targeted for positive sources between 9 and 80V. There is no indication in the part spec of how the positive gate drive is generated (1mA @ 4.5 to 10V), nor is there provision for application of external housekeeping power, or decoupling to avoid lower system voltage issues. Housekeeping supply decoupling is apparently left to the load; something that might be an issue if operating speed was seriously addressed. Turn-on time not specified; turn-off time in the 400nS range.
It may be that a capacitive pump is used to develop power for the gate regulation circuitry, given the drivers current limitations. The housekeeping power, drawn from the Iout pin, must require some serious internal buffering at the higher system voltage, though this again is not illustrated. Linear Vds regulation is attempted around the 25mV level (see previous comment re LTC4354). Elaborate input monitoring and fault indications are present.
LTC4355 data: http://cds.linear.com/docs/Datasheet/4355fe.pdf
LTC4355 app: http://cds.linear.com/docs/Reference%20Design/dc1066A.pdf
LTC4347: is a 6-8 pin ( 5 functional pins) single orring NMOS controller for positive loads between 9 and 80V. It comes close to the requirements of the basic enhanced rectifier application. Housekeeping Vdd is provided through an independent, internally regulated pin. Gate bias is also internally generated (specifically by a charge pump), but does not seem to benefit from an independent Vdd, even for low voltage output operation (possibly an omission in the spec).
For some reason, gate drive modulation and gate drive discharge are illustrated to be independently controlled by parallel controllers using independent references. The discharging controller is described as a comparator. You can see where this might lead to some interesting regulation issues. As with LTC4355 and LTC4354, turn-on time is unspecified: turn-on time is in the 300nS range, but characterized for a range of Cgs.
Compliance of the ĎOUTí (fet drain sense) pin with respect to the ĎINí (fet source sense and gate drive ref), or Vdd, is unspecified. As compliance below ground is minimal, itís unlikely that the controller could be used to control a basic grounded fet rectifier.
LTC4357 data: http://cds.linear.com/docs/Datasheet/4357fd.pdf
LTC4357 app: http://cds.linear.com/docs/Reference%20Design/dc1203A.pdf
LTC4538: is a 16 pin combination orring controller and internal NMOS switch, intended for lower-voltage (<28V) applications. Controller function is configured similarly to the LTC4357, and applications with an independent Vdd supply, for operation with low (<9V) output voltages are conspicuously absent.
Considering the captive NMOS fet, one wonders what point there is, in exposing the gate pin, but then Iím biased against captive power semiconductors, for this function. Using the internal regulation threshold of ~25mV for the internal device provided, the potential advantages of linear gate voltage regulation is lost above 1.5A of output current, in any event.
LTC4538 data: http://cds.linear.com/docs/Datasheet/4358fa.pdf
LM5050: from National Semiconductor is a 6-pin orring controller introduced in Oct 2010, with functionality similar to LTC4357, but no attempt for pin compatability. It adds diagnostic functions via the 6th pin.
LM5050-2 data: http://www.national.com/ds/LM/LM5050-2.pdf
LM5050 app: http://www.national.com/an/AN/AN-2051.pdf
FAN6204: also makes a late entry from Fairchild/Samsung, an SO-8 package with functionality similar to ZXGD3101, with near pin compatibility. It prescribes external resistors in series with the drain voltage sensing terminal.
FAN6204 data: http://www.fairchildsemi.com/ds/FA/FAN6204.pdf
AOZ7200: looks to be the closest to date, offering what is not implicitly linear control, based around roughly -140mV conduction drop.
It promises to turn the fet off at 1mv.
Control power is developed from the <600V 'drain' node, which bleeds current, when required or available, into an external housekeeping storage capacitor. Control functions if the storage cap >18V. I'd like to get my hands on some of these, just to see how fast the controller actually is. SOT23-5.
The AOZ7270 comes with a 600V 190mR NMOS fet in a DNF5x7-12L body.
AOZ7200CI data: http://www.aosmd.com/res/data_sheets/AOZ7200CI.pdf
AOZ7270DI data: http://www.aosmd.com/res/data_sheets/AOZ7270DI.pdf
Think linear, gentlemen.
Normally-Off Synchronous Rectifier Example:
LTspice SwCad IV (spice version4) files are appended to this page which may be useful in demonstrating both the LF ( a 60Hz 12V 24A capacitive filter rectifier) and HF (200KHz 12V full-Wave current doubler) applications of this technique. As well, an integrated model is demonstrated, employing a small-signal high-voltage npn structure in inverted mode, suitable for drain sensing when isolated wells are available.
As the frequency increases, less emphasis is placed on the actual tolerance of the regulated forward voltage drop, and more effort is concentrated on switching speed, gross level detection and drive timing. The integrated version allows regulated voltage sense tailoring, through a simple resistor adjustment.
These demonstrations are only useful in that they show intended function, within the limitations of the basic spice models provided in the SwCad IV package. In fact, just substituting similar components into these files can cause them to malfunction grossly, due to differences or limitations in the model structures. Feel free to contact me for practical circuit application schematics and component types.
LTspice SwCad IV software download : http://www.linear.com/designtools/software/#Spice
60Hz Full Wave Rectifier Application
200KHz Full-wave Current Doubler (Hybridge) Application
(diagram below illustrates one phase)
VDS(M6) below, is amplified by a factor of 10, when refered to the left-hand scale. It should probably be labeled VSD to give a correct polarity convention in the third quadrant.
100KHz Integrated Circuit Modeling Issues:
In this example Q8 operates in inverted mode during synchronous fet conduction. The regulated voltage of the conducting mosfet is set by adjusting R2.
Note: Gate voltage is driven below ground as the drain voltage falls under the external force of inductor current flow, at speeds approaching 1000V/uSec.
The internal fet body diode conducts for 320nSec as the gate voltage slowly rises, driven by 750mA of gate drive - looking like less than 100pF of straight gate capacitance, though the model specifies > 1nF. Gate drive is nonlinear above 18A, as can be seen if the simulation is extended for the full switching period of 10uSec.
This period would normally be expected to introduce charge storage, independent of gate drive control method. However, if the inductor is increased to 5uH and peak turn-on currents are reduced, the current drawn by the source at turn-off actually increases in the simulation.
Gate enhancement, at 4V5, is sufficient to regulate the reverse fet voltage at 160mV prior to turn-off. This enhancement is successfully reduced to 1V prior to fet drain current reversal, in ~6nSec, however significant drain current is still drawn by the source as the fet drain voltage rises at 500v/uSec.
As the inductor increases, reducing peak current, the current at the time of injection/accumulation is reduced, but the peak current drawn by the source actually increases. This is because current drawn during this simulation turn-off is actually a product of internal Rg and applied dv/dt on the drain-gate capacitance. The model fet conducts to limit applied dv/dt.
The level 4 spice model can actually simulate stored charge if the body diode is assigned a TT value, but this is not actually dependant on current levels at the time of charge injection/accumulation. This is just one of the issues that will affect accurate modeling of the integrated version.
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